1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor memory device, and more particularly to a method of fabricating a nonvolatile semiconductor memory device which has floating-gates and is electrically writable and erasable.
2. Description of the Related Art
Electrically writable and erasable nonvolatile semiconductor memory devices (EEPROM) conventionally have two transistors per bit which occupy a large area, resulting in high cost devices. As a result, such devices have been used for limited purposes. In recent years, however, research and development has progressed for a flash EEPROM memory device which use a single transistor per bit. One type of flash memory device is discussed in U.S. Pat. No. 5,280,446.
FIG. 14 is a cross section of a semiconductor memory element discussed in U.S. Pat. No. 5,280,446. In this semiconductor memory element, a first insulating film 42 is formed on a p-type semiconductor substrate 41. Film 42 is obtained by oxidizing the p-type semiconductor substrate 41. A first polysilicon layer (polycrystal silicon layer) 44 which is doped with impurities on the insulating thin film 42, and then a second insulating layer 50 is deposited on the first polysilicon layer 44. The second insulating layer 50 can be a single layer of, for example, silicon oxide (SiO.sub.2) which is formed by oxidizing the first polysilicon layer 44, or the second insulating layer can be a multilayer structure of, for example, ONO. A floating-gate 44 is formed by pattern-etching the second insulating layer 50 and the first polysilicon layer 44, and a control gate 45 is formed by depositing a second polysilicon layer 45 on the second insulating layer 50 and then pattern-etching the second polysilicon layer 45. In other words, the first polysilicon layer serves as the floating-gate 44 and the second polysilicon layer serves as the control gate 45. A laminated structure of the first polysilicon layer, the second insulating layer, and the second polysilicon layer is called a stacked gate structure.
Additionally, a drain 48 and a source 49 are formed on the p-type semiconductor substrate 41 by implanting n-type dopants. Further, a third insulating layer 51 is deposited on the above stacked gate structure. After pattern etching of the insulating layer 51, a select gate 47 is formed so as to cover the control gate electrode 45, the drain 48, and the source 49.
FIG. 15 is an equivalent circuit of the semiconductor memory element shown in FIG. 14. This semiconductor memory element serves as a nonvolatile memory element. In the semiconductor memory element, voltages of 5 V, 12 V, and 2 V are applied to the drain 48, the control gate 45, and the select gate 47, respectively, during programming (a write operation) for the memory element. These applied voltages set the channel region under the floating gate 44 on and a voltage in the source side (point N in FIG. 15) of a floating gate transistor becomes a drain voltage (5 V). On the other hand, a channel region under the select gate 47 is weakly set on, and a drop of the voltage in the channel region under the select gate 47 is small so that a voltage at the point M in FIG. 15 becomes about zero. This causes an electric potential difference between the point M and the point N. This potential difference, increases the speed of channel electrons passing between the point M and the point N so that they are changed to hot electrons.
These hot electrons are implanted into the floating gate 44 by means of a voltage from the control gate 45. As described above, in the configuration shown in FIG. 14, the electrons are implanted into the floating gate 44 from the source side of the floating gate 44. This is known as source side injection. The efficiency of implanting electrons using source side injection is greater than that of implanting electrons from the drain side, which is typically done. Thus, a single power supply can be used with source side injection.
FIGS. 16 and 17 are a sectional view and a plan view, respectively, of a memory cell array (a semiconductor memory device) having a 4.times.4 matrix configuration composed of semiconductor memory elements (memory cells) shown in FIG. 14. In this semiconductor memory device (memory cell array), select gates 47 (SG) are arranged in rows overlaying a plurality of control gates 45 (CG), and a plurality of source and drain lines 48 and 49. Each select gate row extends in a single direction so as to be perpendicular to the control gates 45 and the drain and source gates 48 and 49. The control gate 45, drain lines 48 and the source lines 49 are arranged in alternating columns, each being parallel with the control gates (CG) as seen in FIG. 17.
In this semiconductor memory device, each semiconductor memory element has a floating-gate electrode 44 formed on first insulating thin film (a gate oxidation film) 42 on a semiconductor substrate 41, and a line-shaped control gate electrode 45 covering the floating-gate electrode 44 through a second insulating film 50 (an ONO laminated film). A line-shaped select gate 47 extends over the top and side surfaces of the stacked gate structure which is composed of floating gate 44 and control gate 45 through insulating films, such as films 51 and 50, and over a part of the substrate 41 through the first insulating thin film 42 (a gate oxidation film) on the substrate 41. The stacked gate structure is arranged perpendicular to the select gate 47. Line-shaped substrate diffusion regions (e.g., the source line 49 and the drain line 48) are alternately arranged parallel with the control gate, wherein one of the diffusion regions (the source 49) is offset from the control gate 45 (or the stacked gate structure) so that it is possible to achieve a matrix selection of respective semiconductor memory element regions using the control gate 45 and the select gate 47.
FIG. 18 shows an equivalent circuit of the semiconductor memory device (memory cell array) shown in FIGS. 16 and 17. To select memory cell P1 for a storage operation, a voltage of 5 volts is applied to drain line D1 and source line S2, a voltage of 12 volts is applied to control gates CG1 and CG2, and a voltage of about 2 volts is applied to select gate SG1. Other lines are kept at a grounding potential. The reason for applying 5 volts to the source line S2 is to inhibit a storage operation in an unselected adjacent cell P5 which is in the same line as cell P1. In addition, with a difference of potentials between the drain D1 and the source S2 set to be about 0 volts, hot electrons are inhibited from being generated in the unselected adjacent cell P5. Further, source S2 is not adjacent to the floating-gates and, therefore, blocks noise and the like from occurring.
As described above, the selected memory cell P1 can be used for the storage operation by implanting electrons (hot electrons) from the source side of the floating-gates. Accordingly, this memory circuit can be operated by using a single 5 volt power supply. In addition, an element in the memory cell array can be selected using the control gates (CG) and select gates (SG) shown in FIGS. 16-18. Therefore, in a circuit wired in a contactless NOR system, adjacent memory cells can share a diffusion layer of a source line and a drain line so that the area of the memory array can be reduced.
However, in the above semiconductor memory device (the memory cell array), a rectangular LOCOS (local oxidation structure) 150 is required for separating respective elements (cells) in the memory cell array. This LOCOS structure is shown in FIG. 19. The corners of this rectangular LOCOS 150 are rounded off when miniaturizing the semiconductor memory device. Typically, the rounded off LOCOS is not a problem with semiconductor devices. However, the rounded off LOCOS becomes more of a problem in semiconductor devices classified as 0.35 to 0.4 .mu.m generation devices. When fabricating such devices and in future smaller devices the light wavelength used in a lithographic process is substantially the same as the minimum size of a pattern. Therefore, when fabricating conventional semiconductor memory devices shown in FIGS. 16 and 17, a mask is required that has an overlaying mask matching allowance (X2) between the laminated gate and the LOCOS and an overlaying mask matching allowance (X5) between the source diffusion layer and the LOCOS. However, using conventional fabricating techniques limits the reductions in the overlap allowances between each gate and each LOCOS, and between each diffusion layer and each LOCOS as well as other reductions in other dimensions.